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TOLERA2 (TEC2015-65902)

Variability in Nanometric Technologies: Tolerance, Reliability and Benefits

(Variabilidad en Tecnologías Nanométricas: Tolerancia, Fiabilidad y Aprovechamiento)

Summary

Circuits of current nanometer technologies suffer from great variabiliy both static (process variations) and dynamic (temperature, voltage and aging). Designers can increase reliability of these circutis by implementing specific mechanisms to deal with this variability. In this project we first propose to design and implement robust sensors to be part of variability monitoring networks. A key goal of this project is that the sensors must be aging and radiation tolerant, because both variables significantly affect the performance of nanometric circuits, even at ground level.
 
As pre-fabrication validation support we will develop a complex simulation framework that can systematically and efficiently deal with the three views faced in the project: variability, aging and radiation.
 
There can be also seen a positive side of variability. There are systems that require centain randomness which can be found in the variability suffered by the circuit. This usually happens in authentication or security systems. Another goal of this project is to design two basic primitives in security systems: PUF (Physiscally Unclonable Functions) and RNGs (Random Number Generators) based on variability sensors.
 
Finally, we will explore the potential use of emerging devices taking advantage of the expertise of the research group on modeling and simulation of memristors. We make a step forward and we propose the use of this kind of emerging devices to implement a variability sensor.

Researchers

  • María Luisa López-Vallejo (Investigador principal)
  • Carlos A. López Barrio
  • Pablo Ituero Herrero
  • Fernando García Redondo
  • Javier Agustín Sáenz

Publications

PhD Thesis

Fernando García Redondo, “Resistive RAM: Simulation and Modeling for Reliable Design“, June 2017.

Journal Papers
  1. Self-controlled multilevel writing architecture for fast training in neuromorphic RRAM applications“, F. García-Redondo, M. López-Vallejo. Nanotechnology 29 (40), Jul. 2018.
  2. Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks“, F. García-Redondo, M. López-Vallejo, in IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 65, no. 5, May 2018. doi: 10.1109/TCSI.2017.2755123.
  3. On the Design and Analysis of Reliable RRAM-CMOS Hybrid Circuits“, F. García-Redondo and M. López-Vallejo, IEEE Transactions on Nanotechnology, vol.  16, no. 3, pp. 514-522, July 2017. doi: 10.1109/TNANO.2017.2697311
  4. Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges“, F. García-Redondo, P. Royer, M. López-Vallejo, H. Aparicio, P. Ituero and C. A. López-Barrio, in IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, April 2017. Impact Factor (2014): 1.245. doi: 10.1109/TVLSI.2016.2634083.
  5. A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices“, M. Garrido, M. A. Sánchez, M. L. López-Vallejo and J. Grajal, in IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp. 375-379, Jan. 2017. Impact Factor (2014): 1.245. doi: 10.1109/TVLSI.2016.2567784.
  6. SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds“, F. García-Redondo, R. P. Gowers, A. Crespo-Yepes, M. López-Vallejo and L. Jiang, in IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 63, no. 8, pp. 1255-1264, Aug. 2016. doi: 10.1109/TCSI.2016.2564703.
  7. A performance study of CUDA UVM vs. manual optimizations in a real-world setup: Application to a Monte Carlo wave-particle event-based interaction mode“, J. M. Nadal-Serrano and M. Lopez-Vallejo, IEEE Transactions on Parallel and Distributed Systems, vol. 27, no. 6, June 2016.
Conference papers
  1. “Time-Domain Coding for Resource-Efficient Deep Neural Networks”, S. Avalos-Legaz, P. Ituero. Conference on Design of Circuits and Integrated Systems (DCIS), Nov. 2019.
  2. “A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology”, A. Bahramali, M. Lopez-Vallejo, C. A. Lopez-Barrio, Conference on Design of Circuits and Integrated Systems (DCIS), Nov. 2019.
  3. “Temperature-aware writing architecture for multilevel memristive cells”, A. de Gracia Herranz, M. Lopez-Vallejo. International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodes, Greece, July 2019.
  4. “Performance-oriented Implementation of Hilbert Filters on FPGAs”, D. Fortún, C. G. de la Cueva, J. Grajal, M. López-Vallejo, C. A. Lopez-Barrio, Conference on Design of Circuits and Integrated Systems (DCIS), Nov. 2018.
  5. A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications“, A. Bahramali and M. Lopez-Vallejo, International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 62 – 67, July 2018.
  6. A 40nm Critical Path Monitor for the Detection of Setup and Hold Time Violations“, H. Aparicio and P. Ituero, International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp: 13 – 18, July 2018.
  7. Advanced integration of variability and degradation in RRAM SPICE compact models“, F. García-Redondo; M. López-Vallejo; C. A. López-Barrio, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Italy, June 2017.
  8. “CAS-T Lecture: Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges”, F. García-Redondo, P. Royer, M. López-Vallejo, H. Aparicio, P. Ituero and C. A. López-Barrio, IEEE international Symposium on Circuits and Systems, (ISCAS), Baltimore, MD (USA), May 28-31 2017. 
  9. “CAS-T Lecture: SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds”, F. García-Redondo, R. P. Gowers, A. Crespo-Yepes, M. López-Vallejo and Liudi Jiang, IEEE International Symposium on Circuits and Systems, (ISCAS), Baltimore, MD (USA), May 28-31 2017.
  10. Characterization of analog modules: Reliability analyses of radiation, temperature and variations effects“, F. García-Redondo, H. Aparicio, M. López-Vallejo, P. Ituero and C. López-Barrio, Conference on Design of Circuits and Integrated Systems (DCIS), pp. 1-5, Granada, Nov. 2016.
  11. Reliable design methodology: The combined effect of radiation, variability and temperature“, F. García-Redondo, M. López-Vallejo, H. Aparicio and P. Ituero, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 1-4, Lisbon, 2016.
  12. Taxonomy of power supply monitors and integration challenges“, P. Ituero, M. Lopez-Vallejo, H. Aparicio and F. Garcia-Redondo, International Mixed-Signal Testing Workshop (IMSTW), pp. 1-6, Sant Feliu de Guixols, 2016.
  13. Calibration-free 1052 µm2 power supply monitor“, H. Aparicio, P. Ituero and M. López-Vallejo, Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp.1-4, Lisbon, 2016.
  14. A temperature-independent PUF with a configurable duty cycle of CMOS ring oscillators“, J. Agustin and M. L. Lopez-Vallejo, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2471-2474, Montreal, QC, 2016.