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RAFFTING (PID2021-126991NA-I00)

Realizing Advanced FFT Implementations for 6G (RAFFTING)

Summary

6G will provide ultimate experience for all through hyper-connectivity involving humans and machines, which will be achieved by connecting hundreds of billions of devices. This will require extremely high data rates in the range of 1 Tb/s. Likewise, many applications such as connected autonomous vehicles (CAV) or telesurgery will demand ultra-reliable and low latency communications (URLLC), where a latency below 100 us is expected. On top of it, low power consumption is a must for 6G, where energy efficiency is considered as a key performance indicator (KPI) and is expected to exceed 1 Tb/J.
 
In order to make 6G possible, all the components of the 6G system must be optimized towards these goals. If a single component has high latency, the latency of the entire system may be compromised; and the same occurs for the other two KPIs. Thus, the way to get closer to the performance expected for 6G involves that experts in each of the components of the 6G system provide optimized solutions for these components.
 
The fast Fourier transform (FFT) is a cornerstone for the implementation of communication systems. Therefore, it is essential to study this algorithm in depth and provide solutions that deal with the stringent requirements of 6G communications sytems. Accordingly, the main goal of the RAFFTING project is to break the limitations of current FFT architectures that may hinder the development of 6G. This is achieved by providing significant advancements in three areas of high importance for 6G: Non-power-of-two FFTs, low latency, and low power consumption. 
 

The RAFFTING project has been funded by the Spanish Ministry of Science and Innovation, the AEI, and the European Regional Development Fund through the call “Proyectos de Generación de Conocimiento, 2021”.

Researchers

  • Mario Garrido (PI)
  • Juan Antonio López
  • Pedro Malagón
  • Zeynep Kaya
  • Pedro Paz
  • Víctor Manuel Bautista

Files

The files associated to some of the works in the project can be found at our GitLab Repository FFT Cores.

Publications

Master Theses
  1. Ignacio Amat, “Performance Optimisation of Variable Precision Digital Signal Processing Algorithms”, Master Thesis, Dpt. Electronic Engineering, Universidad Politécnica de Madrid, Feb. 2023.
  2. Jezael Pérez, “Design of Parallel Pipelined FFT Architectures for 6G on FPGAs”, Dpt. of Electronic Engineering, Universidad Politécnica de Madrid, Sep. 2022.
  3. Jason (Chia-Jen) Lee, “A 2k/3×2k-Point Multi-Path Partial FFT Processor and Bit Reversal Circuits for Non-Power-of-Two FFTs”, Institute of Electronics, National Yang Ming Chiao Tung University (Taiwan), Aug. 2022.
  4. Víctor Manuel Bautista, “Design and Implementation of Non-Power-of-Two FFT Architectures for 5G and Beyond”, Dpt. of Electronic Engineering, Universidad Politécnica de Madrid, July 2022.
Journal papers
  1. Víctor Manuel Bautista, Mario Garrido and Marisa López-Vallejo, “Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond”, IEEE Trans. Circuits Syst. I, Vol. 70, No. 10, pp. 3992-4003, Oct 2023. (Open Access in IEEE).
  2. Zeynep Kaya and Mario Garrido, “Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G”, IEEE Trans. Circuits Syst. I, Vol. 70, No. 10, pp. 4004-4014, Oct. 2023. (Open Access in IEEE).
  3. Pedro Paz and Mario Garrido, “CORDIC-Based Computation of Arcsine and Arccosine Functions on FPGA”, IEEE Trans. Circuits Syst. II, Vol. 70, No. 9, pp. 3684-3688,  Sep. 2023. (Open Access in IEEE).
  4. Zeynep Kaya, Mario Garrido and Jarmo Takala, “Memory-Based FFT Architecture with Optimized Number of Multiplexers and Memory Usage”, IEEE Trans. Circuits Syst. II, Vol. 70, No. 8, pp. 3084-3088, Aug. 2023. (Open Access in IEEE).
Conference papers
  1. Víctor Manuel Bautista and Mario Garrido, “An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond”, Conference on Design of Circuits and Integrated Systems, Málaga (Spain), pp. 61-66, Nov. 2023.
  2. Ignacio Amat and Juan Antonio López, “Any-Radix Efficient Fully-Parallel Implementation of the Fast Fourier Transform on FPGAs”, Conference on Design and Integrated Systems, Málaga (Spain), pp. 67-72, Nov. 2023.
  3. Charalampos Eleftheriadis, Mario Garrido and Georgio Karakonstantis, “Energy-Efficient Short-Time Fourier Transform for Partial Window Overlapping”, International Symposium on Circuits and Systems (ISCAS), Monterrey, CA (United States), May 2023.