CMOS integrated circuits fabricated with nanoscale technologies are subject to numerous uncertainties related with second-order effects that were previously negligible but now limit the final performance of the circuit and the manufacturing yield. Such is the case of process variations, or variations in the environmental operating conditions (voltage drops, hot spots, failure due to radiation). In this project we propose circuit level techniques aimed to achieve robust designs able to tolerate PVT variations and radiation. Specifically we propose two main objectives:

 

– To design, simulate and manufacture PVT variations sensors that can be integrated into a variations monitoring network on-chip. The proposal includes critical path sensors (with a double objective, measuring both process and aging variations), static power sensors and VDD sensors. All these sensors have to be small, easily integrated in CMOS, low power and oriented towards the constraints imposed by PVT variations monitoring. The sensors will be integrated into a tester circuit of medium complexity.

 

– To study and provide mechanisms for radiation-tolerant digital circuits by designing and implementing a basic standard cell library radiation hardened. Hardening techniques will be implemented at the physical (layout) and digital level and applied to a reduced set of basic logic gates and flip-flops that must be big enough to satisfy the requirements of the synthesis tools. We will perform an in-depth study of the tradeóff etween area, performance and the degree of radiation toleration.

 

Finally, we propose the design of two sensors, for aging (through critical path) and temperature, employing the developed radiation tolerance techniques. These sensors can be integrated into future applications for high radiation environments, where remote monitoring plays a key role.