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JIN (APOYO-JOVENES-21-TL23SB-116-I4FOMC)

FPGA Implementation of Data-Intensive Algorithms: Neural Networks and FFT

Summary

The goal of this project is to achieve disruptive results in three key areas related to the implementation of data-intensive algorithms on FPGAs:
  1. Design of large and high-throughput FFTs for radio astronomy. In radio astronomy, extremely large FFTs are calculated at high rates. Our goal is to be able to process large FFTs at high throughput rates on a singe field-programmable gate array (FPGA), instead of  using multiple of them. Based on this approach, we expect very high performance together with a drastic reduction in power consumption and cost of the system with respect to current approaches.
  2.  Explore the limits on FFT performance on FPGAs. This goal of the project aims for carrying out phisical real-time experiments on an advanced FPGA platform to determine the highest performance that FFTs on FPGAs can achieve nowadays, and compare them to the results obtained in other platforms. This involves both the implementation of high-throughput FFT architectures and the development of a platform to test these architectures.
  3. Develop area- and power-efficient neural networks on FPGAs. The implementation of FFTs and neural networks share common challenges. Both calculate a large number of sums and multiplication and require a complex data management. Based on our deep knowledge in FFT architectures, in this project we aim for deriving novel architectures for neural networks that reduce the hardware cost and the power consumption, and applying shift-and-add techniques to neural networks to reduce their complexity even further.

This project has been funded by Comunidad de Madrid through the call “Ayudas de Estímulo a la Investigación de Jóvenes Doctores de la Universidad Politécnica de Madrid, 2021”.

Researchers

  • Mario Garrido (PI)
  • Marisa López-Vallejo
  • Pedro Malagón
  • Pedro Paz
  • Martin Kumm
  • Zeynep Kaya
  • Víctor Manuel Bautista
  • Francisco Albertuz

Files

The files associated to some of the works in the project can be found at our GitLab Repository FFT Cores.

Publications

Master Theses
  1. Simón Portela, “Implementation of a PCIe Interface to Transfer Data at High Speed between a Host and an Advanced FPGA”, Dpt. of Electronic Engineering, Universidad Politécnica de Madrid, Sep. 2022.
Journal papers
  1. Zeynep Kaya and Mario Garrido, “Optimized 4-Parallel 1024-Point MSC FFT”, IEEE Access, Vol. 12, pp. 84110-84121, Jun. 2024. (Open Access in IEEE).
  2. Guang-Ting Deng, Mario Garrido, Sau-Gee Chen and Shen-Jui Huang, “Radix-2k MSC FFT Architectures”, IEEE Access, IEEE Access, Vol. 11, pp. 81497-81510, July 2023. (Open Access in IEEE).
  3. Pedro Paz and Mario Garrido, “Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices”, J. Signal Process. Syst, Vol. 95, pp. 543-550, Apr. 2023. (Open Access in Springer).
Conference papers
  1. Pedro Paz and Mario Garrido, “A 12.8-GS/s 32-Parallel 1 Million-Point FFT”, Conference on Desing of Circuits and Integrated Systems, Catania (Italy), Nov. 2024.
  2. Pedro Paz and Mario Garrido, “A 5.2 GSps 8-Parallel 1024-Point MDC FFT”, Conference on Design of Circuits and Integrated Systems, Málaga (Spain), pp. 55-60, Nov. 2023.