Pedro Paz recived the B.Sc. degree in Telecomunications Engineering in 2019 and the M.Sc. degree in Electronic Systems Engineering in 2020, both from Technical University of Madrid (UPM). Since 2020 he works as FPGA Engineer in Indra Sistemas. Since 2021 he is pursuing the Ph.D. part time.
Research
- Fast Fourier Transform
- Signal Processing Architectures
- Hardware Acceleration
- Circuits for data permutation
- Circuits for statistical and mathematical operations
- FPGAs
Teaching
Publications
Pedro Paz and Mario Garrido, “CORDIC-Based Computation of Arcsine and Arccosine Functions on FPGA”, IEEE Trans. Circuits Syst. II, Vol. 70, No. 9, pp. 3684-3688, Sep. 2023 (Open Access in IEEE).
Pedro Paz and Mario Garrido, “Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices”, J. Signal Process. Syst, Vol. 95, pp. 543-550, Apr. 2023. (Open Access in Springer).
Mario Garrido and Pedro Paz. Optimum MDC FFT hardware architectures in terms of delays and multiplexers. IEEE Transactions on Circuits and Systems II: Express Briefs, pages 1–1, 2020. URL: https://doi.org/10.1109%2Ftcsii.2020.3022528, doi:10.1109/tcsii.2020.3022528.
Matías J. Garrido, Fernando Pescador, Miguel Chavarrías, Pedro J. Lobo, César Sanz, and Pedro Paz. An fpga-based architecture for the versatile video coding multiple transform selection core. IEEE Access, 8():81887–81903, 2020. doi:10.1109/ACCESS.2020.2991299.
Pedro Paz and Mario Garrido, “A 5.2 GSps 8-Parallel 1024-Point MDC FFT”, Conference on Design of Circuits and Integrated Systems, Málaga (Spain), pp. 55-60, Nov. 2023.
