Marisa López-Vallejo

Full Professor

Marisa López-Vallejo received the M.S. and the Ph.D. degrees from the Universidad Politécnica de Madrid (UPM), Madrid, Spain, in 1993 and 1999, respectively. She was with Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA, as a Technical Staff Member. She is a Full Professor with the Department of Electronic Engineering, UPM. Her current research interests include low-power, PVT-aware design, efficient architectures for brain-inspired computing, emerging memories, and application-specific high-performance programmable architectures.

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Research

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Teaching

Publications

  1. Amadeo de Gracia Herranz and Marisa Lopez-Vallejo. Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations. Integration, 75:141–149, nov 2020. URL: https://doi.org/10.1016%2Fj.vlsi.2020.07.001, doi:10.1016/j.vlsi.2020.07.001.

  2. Ernesto Pun-Garc\’ıa and Marisa López-Vallejo. A survey of analog-to-digital converters for operation under radiation environments. Electronics, 9(10):1694, oct 2020. URL: https://doi.org/10.3390%2Felectronics9101694, doi:10.3390/electronics9101694.

  3. X. Zhang, J. Grajal, M. López-Vallejo, E. McVay, and T. Palacios. Opportunities and challenges of ambient radio-frequency energy harvesting. Joule, 4(6):1148–1152, 2020.

  4. J.M. Nadal-Serrano, E.G.G. de la Pedrosa, M. Lopez-Vallejo, A. de Guzmán Fernández González, and C. Lopez-Barrio. Simple method to generate calibrated synthetic smoke-like atmospheres at microscopic scale. PLoS ONE, 2019.

  5. A. Bahramali and M. Lopez-Vallejo. A low power rfid based energy harvesting temperature resilient cmos-only reference voltage. Integration, 67:155–161, 2019.

  6. Mario Garrido, Mar\’ıa Luisa López-Vallejo, and Sau-Gee Chen. Guest editorial: special section on fast fourier transform (FFT) hardware implementations. Journal of Signal Processing Systems, 90(11):1581–1582, aug 2018. URL: https://doi.org/10.1007%2Fs11265-018-1396-1, doi:10.1007/s11265-018-1396-1.

  7. F. Garcia-Redondo and M. Lopez-Vallejo. Auto-erasable rram architecture secured against physical and firmware attacks. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(5):1581–1590, 2018.

  8. F. Garcia-Redondo and M. López-Vallejo. Self-controlled multilevel writing architecture for fast training in neuromorphic rram applications. Nanotechnology, 2018.

  9. Mario Garrido, Miguel Angel Sanchez, Maria Luisa Lopez-Vallejo, and Jesus Grajal. A 4096-point radix-4 memory-based FFT using DSP slices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(1):375–379, jan 2017. URL: https://doi.org/10.1109%2Ftvlsi.2016.2567784, doi:10.1109/tvlsi.2016.2567784.

  10. J.M. Nadal-Serrano, A. Nadal-Serrano, and M. Lopez-Vallejo. Democratizing science with the aid of parametric design and additive manufacturing: design and fabrication of a versatile and low-cost optical instrument for scattering measurement. PLoS ONE, 2017.

  11. F. García-Redondo, P. Royer, M. López-Vallejo, H. Aparicio, P. Ituero, and C.A. López-Barrio. Reconfigurable writing architecture for reliable rram operation in wide temperature ranges. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4):1224–1235, 2017.

  12. F. Garcia-Redondo and M. Lopez-Vallejo. On the design and analysis of reliable rram-cmos hybrid circuits. IEEE Transactions on Nanotechnology, 16(3):514–522, 2017.

  13. F. Garcia-Redondo, R.P. Gowers, A. Crespo-Yepes, M. Lopez-Vallejo, and L. Jiang. Spice compact modeling of bipolar/unipolar memristor switching governed by electrical thresholds. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(8):1255–1264, 2016.

  14. J.M. Nadal-Serrano and M. Lopez-Vallejo. A performance study of cuda uvm versus manual optimizations in a real-world setup: application to a monte carlo wave-particle event-based interaction model. IEEE Transactions on Parallel and Distributed Systems, 27(6):1579–1588, 2016.

  15. Javier Agustin, Carlos Gil, Marisa Lopez-Vallejo, and Pablo Ituero. Design and characterization of a built-in cmos tid smart sensor. Ieee Transactions on Nuclear Science, 62(2):443–450, 2015.

  16. V. Iglesias, J. Grajal, M.A. Sanchez, and M. Lopez-Vallejo. Implementation of a real-time spectrum analyzer on fpga platforms. IEEE Transactions on Instrumentation and Measurement, 64(2):338–355, 2015.

  17. J. Agustin, M.L. Lopez-Vallejo, C.G. Soriano, P. Cholbi, L.W. Massengill, and Y.P. Chen. Efficient mitigation of set induced harmonic errors in ring oscillators. IEEE Transactions on Nuclear Science, 62(6):3049–3056, 2015.

  18. J.M. Nadal-Serrano and M. Lopez-Vallejo. A survey on theoretical and practical aspects of imaging aids for artificial vision in professional environments. IEEE Sensors Journal, 15(5):2719–2731, 2015.

  19. J.M. Nadal-Serrano and M. Lopez-Vallejo. A time-resolved monte carlo smoke model for use at optical and infrared frequencies. Fire Safety Journal, 71:299–309, 2015.

  20. V. Iglesias, J. Grajal, P. Royer, M.A. Sánchez, M. López-Vallejo, and O.A. Yeste-Ojeda. Real-time low-complexity automatic modulation classifier for pulsed radar signals. IEEE Transactions on Aerospace and Electronic Systems, 51(1):108–126, 2015.

  21. J. Agustin and M. Lopez-Vallejo. An in-depth analysis of ring oscillators: exploiting their configurable duty-cycle. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(10):2485–2494, 2015.

  22. H. Aparicio, P. Ituero, and M. Lopez-Vallejo. A critical-path monitor for dvfs systems without datapath replication. 2014 Conference on Design of Circuits and Integrated Systems (DCIS). Proceedings, pages 5 pp., 2014.

  23. Carlos Gomez Osuna, Pablo Ituero, and Marisa Lopez-Vallejo. A self-timed multipurpose delay sensor for field programmable gate arrays (fpgas). Sensors, 14(1):129–143, 2014.

  24. Fernando Garcia-Redondo, Marisa Lopez-Vallejo, and Pablo Ituero. Building memristor applications: from device model to circuit design. Ieee Transactions on Nanotechnology, 13(6):1154–1162, 2014.

  25. P. Royer, P. Ituero, M. Lopez-valejo, and C.A.L. Barrio. Implementation tradeoffs of triangle traversal algorithms for graphics processing. 2014 Conference on Design of Circuits and Integrated Systems (DCIS). Proceedings, pages 6 pp., 2014.

  26. I. Herrera-Alzu and M. López-Vallejo. System design framework and methodology for xilinx virtex fpga configuration scrubbers. IEEE Transactions on Nuclear Science, 61(1):619–629, 2014.

  27. P. Royer and M. Lopez-Vallejo. Using pmos pass-gates to boost sram performance by exploiting strain effects in sub-20-nm finfet technologies. IEEE Transactions on Nanotechnology, 13(6):1226–1233, 2014.

  28. Pablo Ituero, Marisa Lopez-Vallejo, and Carlos Lopez-Barrio. A 0.0016 mm(2) 0.64 nj leakage-based cmos temperature sensor. Sensors, 13(9):12648–12662, 2013.

  29. Carlos Benito, Pablo Ituero, Marisa Lopez-Vallejo, JS Matos, and F Leporati. A low-area reference-free power supply sensor. 16th Euromicro Conference on Digital System Design (Dsd 2013), pages 728–733, 2013.

  30. Pablo Ituero and Marisa Lopez-Vallejo. Ratio-based temperature-sensing technique hardened against nanometer process variations. Ieee Sensors Journal, 13(2):442–443, 2013.

  31. F. De Dinechin, P. Echeverría, M. López-Vallejo, and B. Pasca. Floating-point exponentiation units for reconfigurable computing. ACM Transactions on Reconfigurable Technology and Systems, 2013.

  32. I. Herrera-Alzu and M. López-Vallejo. Design techniques for xilinx virtex fpga configuration memory scrubbers. IEEE Transactions on Nuclear Science, 60(1):376–385, 2013.

  33. P. Echeverría and M. López-Vallejo. High performance fpga-oriented mersenne twister uniform random number generator. Journal of Signal Processing Systems, 71(2):105–109, 2013.

  34. F. Garcia-Redondo, M. Lopez-Vallejo, P. Ituero, and C.L. Barrio. A cad framework for the characterization and use of memristor models. 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pages 25–8, 2012.

  35. C. Gomez Osuna, M.A. Sanchez Marcos, P. Ituero, and M. Lopez-Vallejo. A monitoring infrastructure for fpga self-awareness and dynamic adaptation. 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2012), pages 765–8, 2012.

  36. Pablo Ituero, Marisa Lopez-Vallejo, Miguel Angel Sanchez Marcos, and Carlos Gomez Osuna. Light-weight on-chip monitoring network for dynamic adaptation and calibration. Ieee Sensors Journal, 12(6):1736–1745, 2012.

  37. P. Ituero, F. Garcia-Redondo, and M. Lopez-Vallejo. Temperature sensor placement including routing overhead and sampling inaccuracies. 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pages 69–72, 2012.

  38. Emilio Novoa Suner, Pablo Ituero, Marisa Lopez-Vallejo, T Riesgo, and E DelaTorreArnanz. Area-delay trade-offs of texture decompressors for a graphics processing unit. Vlsi Circuits and Systems V, 2011.

  39. P. Ituero, M. Lopez-Vallejo, M.A.S. Marcos, C.G. Osuna, and P. Kitsos. On-chip monitoring: a light-weight interconnection network approach. Proceedings of the 2011 14th Euromicro Conference on Digital System Design. Architectures, Methods and Tools. (DSD 2011), pages 619–25, 2011.

  40. P. Echeverría and M. López-Vallejo. Customizing floating-point units for fpgas: area-performance-standard trade-offs. Microprocessors and Microsystems, 35(6):535–546, 2011.

  41. J.L. Ayala, C. Méndez, and M. López-Vallejo. Thermal analysis and modeling of embedded processors. Computers and Electrical Engineering, 36(1):142–154, 2010.

  42. M. Lopez-Vallejo, A.F. Herrero, P. Ituero, and G. Caffarena. Providing self-learning to students of highly attended electronics courses through the remote access to a microelectronics laboratory. 2009 EAEEIE Annual Conference, pages 6 pp., 2009.

  43. Miguel A. Sanchez, Mario Garrido, Marisa Lopez-Vallejo, and Jesús Grajal. Implementing FFT-based digital channelized receivers on FPGA platforms. IEEE Transactions on Aerospace and Electronic Systems, 44(4):1567–1585, oct 2008. URL: https://doi.org/10.1109%2Ftaes.2008.4667732, doi:10.1109/taes.2008.4667732.

  44. Pablo Ituero, Jose L. Ayala, and Marisa Lopez-Vallejo. A nanowatt smart temperature sensor for dynamic thermal management. Ieee Sensors Journal, 8(11-12):2036–2043, 2008.

  45. Pablo Ituero and Marisa Lopez-Vallejo. Further specialization of clustered vliw processors: a map decoder for software defined radio. Etri Journal, 30(1):113–128, 2008.

  46. P. Echeverría, J.L. Ayala, and M. López-Vallejo. Power considerations in banked cams: a leakage reduction approach. VLSI Design, 2008.

  47. J.L. Ayala, M. Lopez-Vallejo, C.A. López-Barrio, and A. Veidenbaum. A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. International Journal of Embedded Systems, 3(4):285–293, 2008.

  48. D. Atienza, P. Raghavan, J.L. Ayala, G. De Micheli, F. Catthoor, D. Verkest, and M. López-Vallejo. Joint hardware-software leakage minimization approach for the register file of vliw embedded architectures. Integration, the VLSI Journal, 41(1):38–48, 2008.

  49. Pablo Ituero, Jose L. Ayala, Marisa Lopez-Vallejo, and IEEE. Leakage-based on-chip thermal sensor for cmos technology. 2007 Ieee International Symposium on Circuits and Systems, Vols 1-11, pages 3327–3330, 2007.

  50. J.L. Ayala, M. López-Vallejo, D. Atienza, P. Raghavan, F. Catthoor, and D. Verkest. Energy-aware compilation and hardware design for vliw embedded systems. International Journal of Embedded Systems, 3(1-2):73–82, 2007.

  51. Pablo Ituero, Marisa Lopez-Vallejo, and B Werner. New schemes in clustered vliw processors applied to turbo decoding. Ieee 17th International Conference on Application-Specific Systems, Architectures and Processors, Proceedings, pages 291–296, 2006.

  52. J.L. Ayala, A. Veidenbaum, and M. López-Vallejo. Power-aware compilation for register file energy reduction. International Journal of Parallel Programming, 31(6):451–467, 2003.

  53. M. López-Vallejo and J.C. López. On the hardware-software partitioning problem: system modeling and partitioning techniques. ACM Transactions on Design Automation of Electronic Systems, 8(3):269–297, 2003.

  54. J.L. Ayala, A.G. Lomeña, M. López-Vallejo, and A. Fernández. Design of a pipelined hardware architecture for real-time neural network computations. Midwest Symposium on Circuits and Systems, 1:I419–I422, 2002.

  55. M.L. López Vallejo and J.C. López López. Multi-way clustering techniques for system level partitioning. Proceedings of the Annual IEEE International ASIC Conference and Exhibit, pages 242–247, 2001.

  56. L.S. Fernández, G. Koch, N.M. Madrid, M.L.L. Vallejo, C.D. Kloos, and W. Rosenstiel. Hardware-software prototyping from lotos. Design Automation for Embedded Systems, 3(2-3):117–148, 1998.

  1. D. Fortún, C.G. De La Cueva, J. Grajal, M. López-Vallejo, and C.L. Barrio. Performance-oriented implementation of hilbert filters on fpgas. Proceedings – 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018, 2019.

  2. A. De Gracia Herranz and M. Lopez-Vallejo. Temperature-aware writing architecture for multilevel memristive cells. 2019 IEEE 29th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2019, pages 57–62, 2019.

  3. A. Bahramali, M. Lopez-Vallejo, and C.L. Barrio. A 365mv, 13nw cmos-only energy harvested reference voltage for rfid applications in 40nm technology. 2019 34th Conference on Design of Circuits and Integrated Systems, DCIS 2019, 2019.

  4. O. Koufopavlou, G. Theodoridis, M. Lopez-Vallejo, R. Jevtic, and P. Kitsos. Patmos 2019 welcome message. 2019 IEEE 29th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2019, pages I, 2019.

  5. M. Lopez-Vallejo, R. Jevtic, S. Nikolaidis, A. Hatzopoulos, and R. Picos. Welcome message. 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, pages i, 2018.

  6. A. Bahramali and M. Lopez-Vallejo. A temperature variation tolerant cmos-only voltage reference for rfid applications. 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, pages 62–67, 2018.

  7. F. Garcia-Redondo, M. Lopez-Vallejo, and C.L. Barrio. Advanced integration of variability and degradation in rram spice compact models. SMACD 2017 – 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 2017.

  8. F. Garcia-Redondo, H. Aparicio, M. Lopez-Vallejo, P. Ituero, and C. Lopez-Barrio. Characterization of analog modules: reliability analyses of radiation, temperature and variations effects. 2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 – Proceedings, pages 103–108, 2017.

  9. H. Aparicio, P. Ituero, and M. Lopez-Vallejo. 2.64 pj reference-free power supply monitor with a wide temperature range. Proceedings – 2015 6th International Workshop on CMOS Variability, VARI 2015, pages 9–12, 2016.

  10. H. Aparicio, P. Ituero, and M. López-Vallejo. Calibration-free 1052 ?m2 power supply monitor. 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016, 2016.

  11. P. Ituero, M. Lopez-Vallejo, H. Aparicio, and F. Garcia-Redondo. Taxonomy of power supply monitors and integration challenges. 2016 IEEE 21st International Mixed-Signal Testing Workshop, IMSTW 2016, 2016.

  12. F. García-Redondo, M. López-Vallejo, H. Aparicio, and P. Ituero. Reliable design methodology: the combined effect of radiation, variability and temperature. 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016, 2016.

  13. J. Agustin and M.L. Lopez-Vallejo. A temperature-independent puf with a configurable duty cycle of cmos ring oscillators. Proceedings – IEEE International Symposium on Circuits and Systems, 2016-July:2471–2474, 2016.

  14. I. Herrera-Alzu, M. López-Vallejo, and C.G. Soriano. A dual-layer fault manager for systems based on xilinx virtex fpgas. Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, pages 72–75, 2015.

  15. P. Royer, F. Garcia-Redondo, and M. Lopez-Vallejo. Evolution of radiation-induced soft errors in finfet srams under process variations beyond 22nm. Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, pages 112–117, 2015.

  16. F. Garcia-Redondo, M. Lopez-Vallejo, and P. Ituero. A thermal adaptive scheme for reliable write operation on rram based architectures. Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015, pages 367–374, 2015.

  17. Victor Iglesias, Jesus Grajal, Omar Yeste-Ojeda, Mario Garrido, Miguel A. Sanchez, and Marisa Lopez-Vallejo. Real-time radar pulse parameter extractor. In 2014 IEEE Radar Conference. IEEE, may 2014. URL: https://doi.org/10.1109%2Fradar.2014.6875617, doi:10.1109/radar.2014.6875617.

  18. F. García-Redondo, M. López-Vallejo, P. Royer, and J. Agustín. A tool for the automatic analysis of single events effects on electronic circuits. 2014 5th European Workshop on CMOS Variability, VARI 2014, 2014.

  19. P. Royer, M. Lopez-Vallejo, F.G. Redondo, and C.A. López Barrio. Four-injector variability modeling of finfet predictive technology models. 2014 5th European Workshop on CMOS Variability, VARI 2014, 2014.

  20. P. Royer and M. López-Vallejo. A low power 6t-sram using negative bit-line for variability tolerance beyond 22nm node. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pages 37–42, 2013.

  21. P. Royer, P. Zuber, B. Cheng, A. Asenov, and M. Lopez-Vallejo. Circuit-level modeling of finfet sub-threshold slope and dibl mismatch beyond 22nm. International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, pages 204–207, 2013.

  22. M.A. Sánchez, M. López-Vallejo, and C.A. Iglesias. Hardware reuse improvement through the domain specific language dhdl. Proceedings of the 2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012, pages 857–858, 2012.

  23. M.A. S’Nchez, M. Lopez-Vallejo, C.A. Iglesias, and C.A. Lopez-Barrio. Improving hardware reuse through xml-based interface encapsulation. Proceedings – 2012 IEEE 17th International Conference on Engineering of Complex Computer Systems, ICECCS 2012, pages 49–56, 2012.

  24. M. López-Vallejo, P. Ituero, A.F. Herrero, and F. García. Assessing self-learning electronics through the support of remote labs. Proceedings of the IADIS International Conference e-Learning 2011, Part of the IADIS Multi Conference on Computer Science and Information Systems 2011, MCCSIS 2011, 1:446–452, 2011.

  25. J. Grajal, O. Yeste-Ojeda, M.A. Sanchez, M. Garrido, and M. Lopez-Vallejo. Real time fpga implementation of an automatic modulation classifier for electronic warfare applications. European Signal Processing Conference, pages 1514–1518, 2011.

  26. I. Herrera-Alzu and M. López-Vallejo. Cycle-accurate configuration layer model for xilinx virtex fpgas. Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS, pages 182–185, 2011.

  27. P. Echeverría, M. López-Vallejo, W. Bolognesi, and C. López-Barrio. Exploring performance-power trade-offs for look-up tables in sram-based fpgas. 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, pages 423–426, 2009.

  28. A. Fernández-Herrero, I. Elguezábal, and M. López-Vallejo. A web-based environment providing remote access to fpga platforms for teaching digital hardware design. MCCSIS’08 – IADIS Multi Conference on Computer Science and Information Systems; Proceedings of e-Learning 2008, 2:161–165, 2008.

  29. P. Echeverría, M. López-Vallejo, and J.M. Pesquero. Variance reduction techniques for monte carlo simulations. a parameterizable fpga approach. Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, pages 1296–1299, 2008.

  30. M.A. Sánchez, P. Echeverría, F. Mansilla, and M. López-Vallejo. Designing highly parameterized hardware using xhdl. Proceedings – 2008 Forum on Specification, Verification and Design Languages, FDL’08, pages 78–83, 2008.

  31. I. Herrera-Alzu, M.A. Sánchez, M. López-Vallejo, and P. Echeverría. Experimental methodology for power characterization of fpgas. Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, pages 582–585, 2008.

  32. J.L. Ayala, A. Apavatjrut, D. Atienza, and M. López-Vallejo. Exploring temperature-aware design of memory architectures in vliw systems. Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, pages 81–88, 2007.

  33. P. Echeverría and M. López-Vallejo. Fpga gaussian random number generator based on quintic hermite interpolation inversion. Midwest Symposium on Circuits and Systems, pages 871–874, 2007.

  34. P. Raghavan, J.L. Ayala, D. Atienza, F. Catthoor, G. De Micheli, and M. López-Vallejo. Reduction of register file delay due to process variability in vliw embedded processors. Proceedings – IEEE International Symposium on Circuits and Systems, pages 121–124, 2007.

  35. P. Echeverría, J.L. Ayala, and M. López-Vallejo. A banked precomputation-based cam architecture for low-power storage-demanding applications. Proceedings of the Mediterranean Electrotechnical Conference – MELECON, 2006:57–60, 2006.

  36. C. Méndez, J.L. Ayala, and M. López-Vallejo. Target independent thermal modeling for embedded processors. Industrial Embedded Systems – IES’2006, 2006.

  37. P. Echeverría, J.L. Ayala, and M. López-Vallejo. A low-power pipelined cam for high-performance ip routing. Proceedings of the Sixth International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2006 – Final Program and Technical Digest, pages 249–254, 2006.

  38. J.L. Ayala, D. Atienza, P. Raghavan, M. López-Vallejo, and F. Catthoor. Compilation for delay impact minimization in vliw embedded systems. Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, pages 83–90, 2006.

  39. P. Echeverría, J.L. Ayala, and M. López-Vallejo. Leakage energy reduction in banked content addressable memories. Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pages 1196–1199, 2006.

  40. J.L. Ayala, C. Méndez, and M. López-Vallejo. Analysis of the thermal impact of source-code transformations in embedded-processors. Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pages 866–869, 2006.

  41. P. Ituero, M. López-Vallejo, and S.A. Mujtaba. A configurable application specific processor for turbo decoding. Conference Record – Asilomar Conference on Signals, Systems and Computers, 2005:1356–1360, 2005.

  42. J.L. Ayala, D. Atienza, M. López-Vallejo, J.M. Mendías, R. Hermida, and C.A. López-Barrio. Optimal loop-unrolling mechanisms and architectural extensions for an energy-efficient design of shared register files in mpsocs. Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, 2005:65–71, 2005.

  43. J.L. Ayala, M. López-Vallejo, and A. Veidenbaum. Power-aware register renaming in high-performance processors using compiler support. Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, pages 20–27, 2004.

  44. A.G. Lomeña, M. López-Vallejo, Y. Watanabe, and A. Kondratyev. An efficient hash table based approach to avoid state space explosion in history driven quasi-static scheduling. Proceedings -Design, Automation and Test in Europe, DATE, pages 428–433, 2003.

  45. J.L. Ayala, M. López-Vallejo, A. Veidenbaum, and C.A. López. Energy aware register file implementation through instruction predecode. Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, 2003-January:86–96, 2003.

  46. M. López-Vallejo, S.A. Mujtaba, and I. Lee. A low-power architecture for maximum a posteriori decoding. Conference Record of the Asilomar Conference on Signals, Systems and Computers, 1:47–51, 2002.

  47. M.L. López-Vallejo, J. Grajal, and J.C. López. Constraint-driven system partitioning. Proceedings -Design, Automation and Test in Europe, DATE, pages 411–416, 2000.

  1. P. Ituero and M. López-Vallejo. Temperature monitoring issues in nanometer cmos integrated circuits. Advanced Circuits for Emerging Technologies, pages 483–507, 2012.

  2. I. Herrera-Alzu and M. López-Vallejo. Self-reference scrubber for tmr systems based on xilinx virtex fpgas. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 6951 LNCS:133–142, 2011.

  3. J.L. Ayala, M. López-Vallejo, D. Bertozzi, and L. Benini. Soc communication architectures: from interconnection buses to packet-switched nocs. Embedded Systems Design and Verification: Embedded Systems Handbook, Second Edition, pages 14–1–14–29, 2009.

  4. P. Echeverría, D.B. Thomas, M. López-Vallejo, and W. Luk. An fpga run-time parameterisable log-normal random number generator. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 4943 LNCS:221–232, 2008.

  5. P. Ituero, G. Landaburu, J. Del Ser, M. López-Vallejo, P.M. Crespo, V. Atxa, and J. Altuna. Joint source-channel decoding asip architecture for sensor networks. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 4523 LNCS:98–108, 2007.

  6. D. Atienza, P. Raghavan, J.L. Ayala, G. De Micheli, F. Catthoor, D. Verkest, and M. Lopez-Vallejo. Compiler-driven leakage energy reduction in banked register files. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 4148 LNCS:107–116, 2006.

  7. M.A. Sánchez Marcos, ?.F. Herrero, and M. López-Vallejo. Xhdl: extending vhdl to improve core parameterization and reuse. Advances in Design and Specification Languages for SoCs: Selected Contributions from FDL’04, pages 217–235, 2005.

  8. J.L. Ayala, M. López-Vallejo, D. Bertozzi, and L. Benini. State-of-the-art soc communication architectures. Embedded Systems: Handbook, pages 20–1–20–22, 2005.

  9. J.L. Ayala and M. López-Vallejo. A unified framework for power-aware design of embedded systems. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2799:239–248, 2003.

  10. M.L. López-Vallejo, C.A. Iglesias, and J.C. López. Applying the propose&revise strategy to the hardware-software partitioning problem. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 1415:169–179, 1998.

  1. M. López-Vallejo, J.C. López, and C.A. Iglesias. Hardware-software partitioning at the knowledge level. Applied Intelligence, 10(2-3):173–184, 1999.