Juan Antonio López Martín

Associate Professor

Juan A. López received the Ingeniero de Telecomunicación degree from the Universidad de Málaga in 1997, and the Doctor Ingeniero de Telecomunicación degree from the Universidad Politécnica de Madrid (UPM) in 2004. Since November 1997, he has been with the Departamento de Ingeniería Electrónica, UPM, where he is currently an Associate Professor.

He has been a member of more than 30 R&D projects about the development of CAD tools and the implementation of very high-speed digital signal and image processing systems in different applications.

His research interests include design automation, interval methods, and hardware implementation of DSP systems, particularly the fixed-point properties of the linear and non-linear structures, quantization and fast evaluation of the finite word-length effects. He has authored or co-authored more than 30 papers in specialized journals and major congresses of these areas.

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Research

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Teaching

Publications

  1. Pablo Barrio, Carlos Carreras, Juan A. López, Óscar Robles, Ruzica Jevtic, and Roberto Sierra. Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes. Journal of Systems Architecture, 60(7):579–591, aug 2014. URL: https://doi.org/10.1016%2Fj.sysarc.2014.07.001, doi:10.1016/j.sysarc.2014.07.001.

  2. S. Hernandez-Montero, J. A. Lopez, M. Sanchez, L. Esteban, and C. A. Lopez. Real time FPGA-based crosstalk elimination for multichannel interferometry systems in fusion diagnostics. IEEE Transactions on Nuclear Science, 60(5):3585–3591, oct 2013. URL: https://doi.org/10.1109%2Ftns.2013.2272892, doi:10.1109/tns.2013.2272892.

  3. Luis Esteban, J. A. Lopez, E. Sedano, S. Hernandez-Montero, and M. Sanchez. Quantization analysis of the infrared interferometer of the TJ-II stellarator for its optimized FPGA-based implementation. IEEE Transactions on Nuclear Science, 60(5):3592–3596, oct 2013. URL: https://doi.org/10.1109%2Ftns.2013.2278918, doi:10.1109/tns.2013.2278918.

  4. Gabriel Caffarena, Olivier Sentieys, Daniel Menard, Juan A. López, and David Novo. Quantization of VLSI digital signal processing systems. EURASIP Journal on Advances in Signal Processing, feb 2012. URL: https://doi.org/10.1186%2F1687-6180-2012-32, doi:10.1186/1687-6180-2012-32.

  5. Luis Esteban, Miguel Sanchez, Juan Antonio Lopez, Petra Kornejew, Matthias Hirsch, and Octavio Nieto-Taladriz. Development of efficient FPGA-based multi-channel phase meters for IR-interferometers. IEEE Transactions on Nuclear Science, 58(4):1562–1569, aug 2011. URL: https://doi.org/10.1109%2Ftns.2011.2159739, doi:10.1109/tns.2011.2159739.

  6. Gabriel Caffarena, Carlos Carreras, Juan A. López, and Ángel Fernández. SQNR estimation of fixed-point DSP algorithms. EURASIP Journal on Advances in Signal Processing, may 2010. URL: https://doi.org/10.1155%2F2010%2F171027, doi:10.1155/2010/171027.

  7. L. Esteban, M. Sánchez, J. Sánchez, P. Kornejew, M. Hirsch, J. A. López, A. Fernández, and O. Nieto-Taladriz. Continuous phase measurement in the w7-x infrared interferometer by means of a FPGA and high-speed ADCs. Fusion Science and Technology, 58(3):771–777, nov 2010. URL: https://doi.org/10.13182%2Ffst10-9, doi:10.13182/fst10-9.

  8. L. Esteban, M. Sánchez, J.A. López, O. Nieto-Taladriz, and J. Sánchez. Continuous plasma density measurement in TJ-II infrared interferometer—advanced signal processing based on FPGAs. Fusion Engineering and Design, 85(3-4):328–331, jul 2010. URL: https://doi.org/10.1016%2Fj.fusengdes.2010.03.036, doi:10.1016/j.fusengdes.2010.03.036.

  9. Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, and Octavio Nieto-Taladriz. Architectural synthesis of fixed-point DSP datapaths using FPGAs. International Journal of Reconfigurable Computing, 2009:1–14, 2009. URL: https://doi.org/10.1155%2F2009%2F703267, doi:10.1155/2009/703267.

  10. J.A. Lo\’pez, G. Caffarena, C. Carreras, and O. Nieto-Taladriz. Fast and accurate computation of the round-off noise of linear time-invariant systems. IET Circuits, Devices & Systems, 2(4):393, 2008. URL: https://doi.org/10.1049%2Fiet-cds%3A20070198, doi:10.1049/iet-cds:20070198.

  11. Juan A. Lopez, Carlos Carreras, and Octavio Nieto-Taladriz. Improved interval-based characterization of fixed-point LTI systems with feedback loops. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(11):1923–1933, nov 2007. URL: https://doi.org/10.1109%2Ftcad.2007.896306, doi:10.1109/tcad.2007.896306.

  12. Gabriel Caffarena, Olivier Sentieys, Daniel Menard, Juan Antonio Lopez, and David Novo. Quantization of VLSI digital signal processing systems. EURASIP Journal on Advances in Signal Processing, 2012:1–2, February 2012. URL: https://hal.inria.fr/hal-00743410.

  1. S. Hernandez-Montero, J. A. Lopez, M. Sanchez, and L. Esteban. Real time FPGA-based crosstalk elimination for multichannel interferometry systems in fusion diagnostics. In 2012 18th IEEE-NPSS Real Time Conference. IEEE, jun 2012. URL: https://doi.org/10.1109%2Frtc.2012.6418377, doi:10.1109/rtc.2012.6418377.

  2. Gabriel Caffarena, Ángel Fernández-Herrero, Juan A. López, and Carlos Carreras. Fast Fixed-Point Optimization of DSP Algorithms. In José L. Ayala, David Atienza Alonso, and Ricardo Reis, editors, 18th International Conference on Very Large Scale Integration (VLSISOC), volume AICT-373 of VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 182–205. Madrid, Spain, September 2010. Springer. URL: https://hal.inria.fr/hal-01515996, doi:10.1007/978-3-642-28566-0\_8.

  3. Gabriel Caffarena, Carlos Carreras, Juan A. Lopez, and Angel Fernandez. Fast fixed-point optimization of DSP algorithms. In 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip. IEEE, sep 2010. URL: https://doi.org/10.1109%2Fvlsisoc.2010.5642659, doi:10.1109/vlsisoc.2010.5642659.

  4. Gabriel Caffarena, Juan Lopez, Carlos Carreras, and Octavio Nieto-Taladriz. Optimized synthesis of DSP cores combining logic-based and embedded FPGA resources. In 2006 International Symposium on System-on-Chip. IEEE, nov 2006. URL: https://doi.org/10.1109%2Fissoc.2006.321978, doi:10.1109/issoc.2006.321978.

  5. Gabriel Caffarena, Juan Lopez, Carlos Carreras, and Octavio Nieto-Taladriz. High-level synthesis of multiple word-length DSP algorithms using heterogeneous-resource FPGAs. In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. URL: https://doi.org/10.1109%2Ffpl.2006.311288, doi:10.1109/fpl.2006.311288.

  1. Daniel Menard, Gabriel Caffarena, Juan Antonio Lopez, David Novo, and Olivier Sentieys. Fixed-point refinement of digital signal processing systems. In Digitally Enhanced Mixed Signal Systems, number Chapter 1, pages 1–37. The Institution of Engineering and Technology, May 2019. URL: https://hal.inria.fr/hal-01941898, doi:10.1049/PBCS040E\_ch.

  2. Daniel Ménard, Gabriel Caffarena, Juan Antonio Lopez, David Novo, and Olivier Sentieys. Analysis of Finite Word-Length Effects in Fixed-Point Systems. In Shuvra S. Bhattacharyya, editor, Handbook of Signal Processing Systems, pages 1063–1101. 2019. URL: https://hal.inria.fr/hal-01941888, doi:10.1007/978-3-319-91734-4\_29.