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Carlos A. López Barrio

Emeritus Professor
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Office: C-222

Carlos A. López Barrio received the Engineering (equivalent to M.Sc.) and the PhD. degrees in Telecommunication Engineering from the Universidad Politécnica de Madrid (UPM – Technical Univ. of Madrid), Spain, in 1975 and 1977 respectively. He is Full Professor with the Department of Electronic Engineering (UPM), Director of the “Integrated Systems Laboratory –LSI-” Research Group and Board Member of the IPTC (Information Technologies and Telecommunications R&D Center). He has held professional posts at Telefónica (Telecom Operator): Director of Innovation (R&D Subsidiary, Spain), from 1988 to 1997, and Deputy General Director of Technology and Networks (Corporate and Spanish Subsidiary), from 1997-2004. He was Head of the Electronics Engineering Department (UPM, 1982-86 and 2012-2018), General Coordinator of the Moncloa’s Campus of International Excellence (UPM and Complutense Universities) in 2010, and he is nowadays Director of the ITC Doctoral Area (International Doctoral School of the UPM). He has participated in and led a number of national and international research projects. His research interests include efficient architectures for optimal IC and FPGA implementation and high-performance digital architectures, as well as Innovation management.

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Research

  • Signal Processing Architectures
  • Energy Efficiency
  • FPGAs
  • Innovation management
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Teaching

  • INTN: Technological and business innovation
  • MCHP: Methodology, Quality and Personal Skills
  • CRIN: Creativity and Innovation

Publications

  1. J.M. Nadal-Serrano, E.G.G. de la Pedrosa, M. Lopez-Vallejo, A. de Guzmán Fernández González, and C. Lopez-Barrio. Simple method to generate calibrated synthetic smoke-like atmospheres at microscopic scale. PLoS ONE, 2019.

  2. F. García-Redondo, P. Royer, M. López-Vallejo, H. Aparicio, P. Ituero, and C.A. López-Barrio. Reconfigurable writing architecture for reliable rram operation in wide temperature ranges. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4):1224–1235, 2017.

  3. R. Sierra, C. Carreras, G. Caffarena, and C.A.L. Bario. A formal method for optimal high-level casting of heterogeneous fixed-point adders and subtractors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(1):52–63, 2015.

  4. S. Hernandez-Montero, J. A. Lopez, M. Sanchez, L. Esteban, and C. A. Lopez. Real time FPGA-based crosstalk elimination for multichannel interferometry systems in fusion diagnostics. IEEE Transactions on Nuclear Science, 60(5):3585–3591, oct 2013. URL: https://doi.org/10.1109%2Ftns.2013.2272892, doi:10.1109/tns.2013.2272892.

  5. Pablo Ituero, Marisa Lopez-Vallejo, and Carlos Lopez-Barrio. A 0.0016 mm(2) 0.64 nj leakage-based cmos temperature sensor. Sensors, 13(9):12648–12662, 2013.

  6. J.L. Ayala, M. Lopez-Vallejo, C.A. López-Barrio, and A. Veidenbaum. A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. International Journal of Embedded Systems, 3(4):285–293, 2008.

  7. A. Santos, C. López Barrio, and A. García Guerra. Automatic data acquisition system for a photovoltaic solar plant. Solar and Wind Technology, 3(4):259–265, 1986.

  1. A. Bahramali, M. Lopez-Vallejo, and C. Lopez Barrio. An ultra-low power deep sub-micron fast start-up circuit with added line regulation. 2020 35th Conference on Design of Circuits and Integrated Systems, DCIS 2020, 2020.

  2. D. Fortún, C.G. De La Cueva, J. Grajal, M. López-Vallejo, and C.L. Barrio. Performance-oriented implementation of hilbert filters on fpgas. Proceedings – 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018, 2019.

  3. A. Bahramali, M. Lopez-Vallejo, and C.L. Barrio. A 365mv, 13nw cmos-only energy harvested reference voltage for rfid applications in 40nm technology. 2019 34th Conference on Design of Circuits and Integrated Systems, DCIS 2019, 2019.

  4. F. Garcia-Redondo, M. Lopez-Vallejo, and C.L. Barrio. Advanced integration of variability and degradation in rram spice compact models. SMACD 2017 – 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 2017.

  5. F. Garcia-Redondo, H. Aparicio, M. Lopez-Vallejo, P. Ituero, and C. Lopez-Barrio. Characterization of analog modules: reliability analyses of radiation, temperature and variations effects. 2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 – Proceedings, pages 103–108, 2017.

  6. P. Royer, P. Ituero, M. Lopez-valejo, and C.A.L. Barrio. Implementation tradeoffs of triangle traversal algorithms for graphics processing. 2014 Conference on Design of Circuits and Integrated Systems (DCIS). Proceedings, pages 6 pp., 2014.

  7. P. Royer, M. Lopez-Vallejo, F.G. Redondo, and C.A. López Barrio. Four-injector variability modeling of finfet predictive technology models. 2014 5th European Workshop on CMOS Variability, VARI 2014, 2014.

  8. F. Garcia-Redondo, M. Lopez-Vallejo, P. Ituero, and C.L. Barrio. A cad framework for the characterization and use of memristor models. 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pages 25–8, 2012.

  9. M.A. S’Nchez, M. Lopez-Vallejo, C.A. Iglesias, and C.A. Lopez-Barrio. Improving hardware reuse through xml-based interface encapsulation. Proceedings – 2012 IEEE 17th International Conference on Engineering of Complex Computer Systems, ICECCS 2012, pages 49–56, 2012.

  10. P. Echeverría, M. López-Vallejo, W. Bolognesi, and C. López-Barrio. Exploring performance-power trade-offs for look-up tables in sram-based fpgas. 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, pages 423–426, 2009.

  11. M.A. Sanchez, M. Garrido, M. Vallejo, and C. Lopez-Barrio. Automated design space exploration of FPGA-based FFT architectures based on area and power estimation. In 2006 IEEE International Conference on Field Programmable Technology. IEEE, dec 2006. URL: https://doi.org/10.1109%2Ffpt.2006.270303, doi:10.1109/fpt.2006.270303.

  12. J.L. Ayala, D. Atienza, M. López-Vallejo, J.M. Mendías, R. Hermida, and C.A. López-Barrio. Optimal loop-unrolling mechanisms and architectural extensions for an energy-efficient design of shared register files in mpsocs. Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, 2005:65–71, 2005.

  13. J.L. Ayala, M. López-Vallejo, A. Veidenbaum, and C.A. López. Energy aware register file implementation through instruction predecode. Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, 2003-January:86–96, 2003.

  14. Miguel A. Miranda and Carlos A. Lopez-Barrio. Generation of optimized single distributions of weights for random built-in self-test. Proceedings of the International Test Conference, pages 1023–1030, 1993.

  15. M.J. Auado, M.A. Miranda, E. de la Torre, and C. Lopez-Barrio. Dynamic communication strategy for the distributed atpg system dplaton. European Design Automation Conference – Proceedings, pages 271–276, 1993.

  16. M.J. Aguado, E. de la Torre, M.A. Miranda, and C. Lopez-Barrio. Distributed implementation of an atpg system using dynamic fault allocation. Proceedings of the International Test Conference, pages 409–418, 1993.

  1. J.M. Moya, J. Rodríguez, J. Martín, J.C. Vallejo, P. Malagón, A. Araujo, J.-M. De Goyeneche, A. Rubio, E. Romero, D. Villanueva, O. Nieto-Taladriz, and C.A.L. Barrio. Soru: a reconfigurable vector unit for adaptable embedded systems. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 5453:255–260, 2009.