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Carlos Carreras

Full Professor

Carlos Carreras received engineering and M.S. degrees in electrical engineering from the Universidad Politécnica de Madrid (U.P.M.) in 1986 and the University of Texas at Austin in 1989, respectively. He received his Ph.D. degree also from U.P.M. in 1993. From 1987 to 1991 he was a Staff member at Honeywell Bull (Madrid) and Schlumberger Well Services (Austin, TX). Since 1991, he is with the Electrical Engineering Department at UPM, where he currently is a Full Professor. He has actively participated in a number of national and international research projects in the fields of implementation of signal processing circuits, CAD tools development, and hardware acceleration. He is also co-author of multiple publications in these fields. His current research interests are in the areas of architecture and electronic design of high-performance processing systems and accelerators, and CAD tools for system design.






  1. R. Sierra, C. Carreras, and G. Caffarena. Witelo: automated generation and timing characterization of distributed-control macroblocks for high-performance fpga designs. Integration, 68:1–11, 2019.

  2. R. Sierra, C. Carreras, G. Caffarena, and C.A.L. Bario. A formal method for optimal high-level casting of heterogeneous fixed-point adders and subtractors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(1):52–63, 2015.

  3. P. Barrio, C. Carreras, J.A. López, ?. Robles, R. Jevtic, and R. Sierra. Memory optimization in fpga-accelerated scientific codes based on unstructured meshes. Journal of Systems Architecture, 60(7):579–591, 2014.

  4. B. Jovanovic, R. Jevtic, and C. Carreras. Binary division power models for high-level power estimation of fpga-based dsp circuits. IEEE Transactions on Industrial Informatics, 10(1):393–398, 2014.

  5. R. Jevtic and C. Carreras. A complete dynamic power estimation model for data-paths in fpga dsp designs. Integration, the VLSI Journal, 45(2):172–185, 2012.

  6. J. González-Bayón, A. Fernández-Herrero, and C. Carreras. A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e ofdma. Eurasip Journal on Advances in Signal Processing, 2012.

  7. J. González-Bayón, A. Fernández-Herrero, and C. Carreras. Evaluation of rapid prototyping solutions for a 802.16d frequency offset estimation scheme. Journal of Circuits, Systems and Computers, 2012.

  8. R. Jevtic and C. Carreras. Power measurement methodology for fpga devices. IEEE Transactions on Instrumentation and Measurement, 60(1):237–247, 2011.

  9. G. Caffarena, C. Carreras, J.A. Lpez, and ?. Fernández. Sqnr estimation of fixed-point dsp algorithms. Eurasip Journal on Advances in Signal Processing, 2010.

  10. J. González-Bayón, A. Fernández-Herrero, and C. Carreras. Improved schemes for tracking residual frequency offset in dvb-t systems. IEEE Transactions on Consumer Electronics, 56(2):415–422, 2010.

  11. B. Jovanovic, R. Jevtic, and C. Carreras. Triple-bit method for power estimation of nonlinear digital circuits in fpgas. Electronics Letters, 46(13):903–905, 2010.

  12. R. Jevtic and C. Carreras. Power estimation of embedded multiplier blocks in fpgas. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(5):835–839, 2010.

  13. J. González-Bayón, C. Carreras, and O. Edfors. A multistandard frequency offset synchronization scheme for 802.11n, 802.16d, lte, and dvb-t/h systems. Journal of Computer Systems, Networks, and Communications, 2010.

  14. R. Jevtic, C. Carreras, and G. Caffarena. Fast and accurate power estimation of fpga dsp components based on high-level switching activity models. International Journal of Electronics, 95(7):653–668, 2008.

  15. J.A. López, G. Caffarena, C. Carreras, and O. Nieto-Taladriz. Fast and accurate computation of the round-off noise of linear time-invariant systems. IET Circuits, Devices and Systems, 2(4):393–408, 2008.

  16. G. Caffarena, C. Pedreira, C. Carreras, S. Bojanic, and O. Nieto-Taladriz. Fpga acceleration for dna sequence alignment. Journal of Circuits, Systems and Computers, 16(2):245–266, 2007.

  17. J.A. López, C. Carreras, and O. Nieto-Taladriz. Improved interval-based characterization of fixed-point lti systems with feedback loops. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(11):1923–1933, 2007.

  18. N. Ivanovi?, I. Radisavljevi?, D. Marjanovi?, S. Bojani?, and C. Carreras. Molecular size and conformational effects on oligophenylene’s electronic and vibrational properties. Journal of Polymer Science, Part B: Polymer Physics, 44(13):1783–1794, 2006.

  19. I.D. Walker, C. Carreras, R. McDonnell, and G. Grimes. Extension versus bending for continuum robots. International Journal of Advanced Robotic Systems, 3(2):171–178, 2006.

  20. G. Caffarena, C. Carreras, O. Nieto-Taladriz, G.A. Constantinides, and P.Y.K. Cheung. Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(5):339–343, 2006.

  21. J.A. Lopez, G. Caffarena, C. Carreras, and O. Nieto-Taladriz. Optimizing the hardware implementation of constant coefficient dividers using the properties of the quantization operations. WSEAS Transactions on Circuits and Systems, 4(5):462–470, 2005.

  22. C. Carreras and I.D. Walker. Interval methods for fault-tree analysis in robotics. IEEE Transactions on Reliability, 50(1):3–11, 2001.

  23. C. Carreras and I.D. Walker. On interval methods applied to robot reliability quantification. Reliability Engineering and System Safety, 70(3):291–303, 2000.

  24. Carlos Carreras and Juan P. Clar. Designing a complete range of trucks of 13-44 ton gvw. SAE Prepr, 1973.

  1. R. Sierra, F. Mangani, C. Carreras, and G. Caffarena. High-performance decoding of variable-length memory data packets for fpga stream processing. Proceedings – 29th International Conference on Field-Programmable Logic and Applications, FPL 2019, pages 307–313, 2019.

  2. R. Sierra, C. Carreras, and G. Caffarena. Automated timing characterization of high-performance macroblocks for latency insensitive fpga designs. 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, pages 7–12, 2018.

  3. J.A. Lopez, G. Caffarena, C. Carreras, and O. Nieto-Taladriz. Analysis of limit cycles by means of affine arithmetic computer-aided tests. European Signal Processing Conference, 06-10-September-2004:991–994, 2015.

  4. G. Caffarena, A. Fernandez, C. Carreras, and O. Nieto-Taladriz. Fixed-point refinement of ofdm-based adaptive equalizers: an heuristic approach. European Signal Processing Conference, 06-10-September-2004:1353–1356, 2015.

  5. E. Sedano, J.A. López, and C. Carreras. Acceleration of monte-carlo simulation-based quantization of dsp systems. 2012 19th International Conference on Systems, Signals and Image Processing, IWSSIP 2012, pages 189–192, 2012.

  6. E. Sedano, J.A. López, and C. Carreras. A fast interpolative wordlength optimization method for dsp systems. SPL 2012 – 8th Southern Programmable Logic Conference, 2012.

  7. P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl. Turning control flow graphs into function calls: code generation for heterogeneous architectures. Proceedings of the 2012 International Conference on High Performance Computing and Simulation, HPCS 2012, pages 559–565, 2012.

  8. A. Fernández-Herrero, C. Fernández, C. Carreras, P. Zumel, A. Lázaro, and A. Barrado. Use of multisine excitations for frequency-response measurement of nonlinear dc-dc switching converters. Conference Proceedings – IEEE Applied Power Electronics Conference and Exposition – APEC, pages 735–739, 2012.

  9. P. Barrio and C. Carreras. Mesh traversal and sorting for efficient memory usage in scientific codes. Conference Proceedings of the IEEE International Performance, Computing, and Communications Conference, 2011.

  10. R. Jevtic, B. Jovanovic, and C. Carreras. Power estimation of dividers implemented in fpgas. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pages 313–318, 2011.

  11. G. Caffarena and C. Carreras. Precision-wise architectural synthesis of dsp circuits. European Signal Processing Conference, pages 562–566, 2010.

  12. G. Caffarena, J.A. López, A. Fernández-Herrero, and C. Carreras. Sqnr estimation of non-linear fixed-point algorithms. European Signal Processing Conference, pages 522–526, 2010.

  13. G. Caffarena, C. Carreras, J.A. López, and A. Fernández. Fast fixed-point optimization of dsp algorithms. Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010, pages 195–200, 2010.

  14. J. González-Bayón, A. Fernández-Herrero, and C. Carreras. Fast and accurate frequency offset tracking scheme for ofdm dvb-t standard. ICCE 2010 – 2010 Digest of Technical Papers International Conference on Consumer Electronics, pages 123–124, 2010.

  15. G. Caffarena and C. Carreras. Architectural synthesis of dsp circuits under simultaneous error and time constraints. Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010, pages 322–327, 2010.

  16. V. Pejovi?, S. Bojani?, C. Carreras, and A. Badii. A practical method for testing high-speed networking hardware architectures. Proceedings of the 5th International Conference on Networking and Services, ICNS 2009, pages 122–130, 2009.

  17. R. Jevtic, C. Carreras, and V. Pejovic. Floorplan-based fpga interconnect power estimation in dsp circuits. International Workshop on System Level Interconnect Prediction, SLIP, pages 53–60, 2009.

  18. G. Caffarena, J.A. López, G. Leyva, C. Carreras, and O. Nieto-Taladriz. Optimized architectural synthesis of fixed-point datapaths. Proceedings – 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008, pages 85–90, 2008.

  19. R. Jevtic, C. Carreras, and D. Helms. A comparison of approaches for high-level power estimation of lut-based dsp components. Proceedings – 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008, pages 361–366, 2008.

  20. E. Andrés, C. Carreras, G. Caffarena, M. Del Carmen Molinax, O. Nieto-Taladriz, and F. Palaciosk. A methodology for cfd acceleration through reconfigurable hardware. 46th AIAA Aerospace Sciences Meeting and Exhibit, 2008.

  21. J. González-Bayón, C. Carreras, and A. Fernández-Herrero. A comparison of frequency offset synchronization algorithms for wimax ofdm systems. EUROCON 2007 – The International Conference on Computer as a Tool, pages 997–1004, 2007.

  22. J. González-Bayón, C. Carreras, and A. Fernández-Herrero. Comparative evaluation of carrier frequency offset tracking schemes for wimax ofdm systems. ISSPIT 2007 – 2007 IEEE International Symposium on Signal Processing and Information Technology, pages 479–484, 2007.

  23. V. Pejovi?, S. Bojani?, and C. Carreras. Adding value to tcp/ip based information exchange security by specialised hardware. Proceedings – The International Conference on Emerging Security Information, Systems, and Technologies, SECURWARE 2007, pages 145–150, 2007.

  24. R. Jevtic, C. Carreras, and G. Caffarena. Switching activity models for power estimation in fpga multipliers. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 4419 LNCS:201–213, 2007.

  25. V. Pejovi?, S. Bojani?, C. Carreras, and O. Nieto-Taladriz. Detecting masquerading attack in software and in hardware. Proceedings of the Mediterranean Electrotechnical Conference – MELECON, 2006:836–838, 2006.

  26. G. Caffarena, J.A. López, C. Carreras, and O. Nieto-Taladriz. High-level synthesis of multiple word-length dsp algorithms using heterogeneous-resource fpgas. Proceedings – 2006 International Conference on Field Programmable Logic and Applications, FPL, pages 675–678, 2006.

  27. G. Caffarena, J.A. López, C. Carreras, and O. Nieto-Taladriz. Optimized synthesis of dsp cores combining logic-based and embedded fpga resources. 2006 International Symposium on System-on-Chip, SOC, 2006.

  28. G. Leyva, G. Caffarena, C. Carreras, and O. Nieto-Taladriz. A generator of high-speed floating-point modules. Proceedings – 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004, pages 306–307, 2004.

  29. J.A. López, G. Caffarena, C. Carreras, and O. Nieto-Taladriz. Characterization of the quantization properties of similarity-related dsp structures by means of interval simulations. Conference Record of the Asilomar Conference on Signals, Systems and Computers, 2:2208–2212, 2003.

  30. J.A. López, C. Carreras, G. Caffarena, and O. Nieto-Taladriz. Fast characterization of the noise bounds derived from coefficient and signal quantization. Proceedings – IEEE International Symposium on Circuits and Systems, 2003.

  31. J.A. López, C. Carreras, and O. Nieto-Taladriz. Prototyping design of a transceiver for the new double bitrate dect. Midwest Symposium on Circuits and Systems, 1:368–372, 2001.

  32. C. Carreras and I.D. Walker. Sensitivity to parametric uncertainty in robot impact. IEEE/ASME International Conference on Advanced Intelligent Mechatronics, AIM, 2:701–706, 2001.

  33. Carlos Carreras and Ian D. Walker. Interval methods for improved robot reliability estimation. Proceedings of the Annual Reliability and Maintainability Symposium, pages 22–27, 2000.

  34. C. Carreras and M.V. Hermenegildo. Grid-based histogram arithmetic for the probabilistic analysis of functions. Lecture Notes in Artificial Intelligence (Subseries of Lecture Notes in Computer Science), 1864:107–123, 2000.

  35. C. Carreras, J.A. López, and O. Nieto-Taladriz. Bit-width selection for data-path implementations. Proceedings of the International Symposium on System Synthesis, 1999.

  36. C. Carreras, J.C. Lopez, M.L. Lopez, C. Delgado-Kloos, N. Martinez, and L. Sanchez. Co-design methodology based on formal specification and high-level estimation. Hardware/Software Codesign – Proceedings of the International Workshop, pages 28–35, 1996.

  1. G. Caffarena, ?. Fernández-Herrero, J.A. López, and C. Carreras. Fast fixed-point optimization of dsp algorithms. IFIP Advances in Information and Communication Technology, 373:183–205, 2012.

  2. S. Bojani?, V. Pejovi?, G. Caffarena, V. Milovanovi?, C. Carreras, and J. Popovi? Behavioural biometrics hardware based on bioinformatics matching. Advances in Intelligent and Soft Computing, 63 AISC:171–178, 2009.

  3. R. Jevtic and C. Carreras. Analytical high-level power model for lut-based components. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 5349 LNCS:369–378, 2009.

  4. C. Carreras, C.A. López, and M. Hermenegildo. Analytic model of a cache only memory architecture. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 817 LNCS:336–350, 1994.

  1. Javier González Bayón, Carlos Carreras Vaquer, and Angel Fernández Herrero. Frequency synchronization for OFDM/OFDMA systems. In Advances in Wireless Technologies and Telecommunication, pages 216–236. IGI Global, 2012. URL:, doi:10.4018/978-1-4666-0083-6.ch009.

  2. Angel Fernández Herrero, Gabriel Caffarena Fernández, Alberto Jiménez Pacheco, Juan Antonio López Mart\’ın, Carlos Carreras Vaquer, and Francisco Javier Casajús Quirós. Design and implementation of hardware modules for baseband processing in radio transceivers. In Advances in Wireless Technologies and Telecommunication, pages 266–286. IGI Global, 2012. URL:, doi:10.4018/978-1-4666-0083-6.ch011.

  3. G. Leyva, G. Caffarena, C. Carreras, and O. Nieto-Taladriz. Design of prototyping boards with xilinx FPGAS. In Microelectronics Education, pages 81–85. Springer Netherlands, 2004. URL:, doi:10.1007/978-1-4020-2651-5_14.

  4. L. Sánchez, M. L. López, N. Mart\’ınez, C. Carreras, J. C. López, C. Delgado-Kloos, A. Royo, and P. T. Breuer. Co-design at work: the ethernet bridge case study. In Current Issues in Electronic Modeling, pages 125–143. Springer US, 1997. URL:, doi:10.1007/978-1-4757-2629-9_6.