Amadeo de Gracia Herranz
Amadeo de Gracia Herranz received the Bachelor of Engineering in Telecommunication Technologies and Services Engineering in February 2017 and their Master of Science in Telecommunication Engineering in February 2019 from the Technical University of Madrid (UPM) and he works on his Phd since then. His research focuses on read-write memristor drivers and in-memory computing. He is assistant professor from September 2020.
As an student he was strongly related to IEEEsb of Madrid and he is now part of the IEEE Young Professionals Spanish team. He moved to Sweden with Erasmus+ program during half a year in Linöping University.
Amadeo Gracia De Herranz and Marisa Lopez-Vallejo. Time to digital sensing for multilevel RRAM cells. IEEE Access, 9:160216–160223, 2021. URL: https://doi.org/10.1109%2Faccess.2021.3132202, doi:10.1109/access.2021.3132202.
Amadeo de Gracia Herranz and Marisa Lopez-Vallejo. Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations. Integration, 75:141–149, nov 2020. URL: https://doi.org/10.1016%2Fj.vlsi.2020.07.001, doi:10.1016/j.vlsi.2020.07.001.